• DocumentCode
    3474813
  • Title

    A small-area high-performance 512-point 2-dimensional FFT single-chip processor

  • Author

    Miyarnoto, N. ; Kaman, L. ; Maruo, K. ; Kotani, K. ; Ohmi, T.

  • Author_Institution
    University of Tohoku
  • fYear
    2004
  • fDate
    27-30 Jan. 2004
  • Firstpage
    537
  • Lastpage
    538
  • Abstract
    We have designed an FFT processor based on the 2-stage cached-memory architecture, which integrates 552,000 transistors within an area of 2.8 x 2.8 mm2 with CMOS 0.35μm triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, I-dimensonnl FFT in 23.2 μsec and a 2-dimensional one in only 23.8 msec at 133MHz operation. We have measured this processor consumes 439.6mW at 33V, lOOMHz operation.
  • Keywords
    CMOS process; Computer architecture; Design engineering; Discrete Fourier transforms; Hardware; Laboratories; Multidimensional signal processing; Process design; Registers; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
  • Conference_Location
    Yohohama, Japan
  • Print_ISBN
    0-7803-8175-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2004.1337637
  • Filename
    1337637
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3474813