CMOS Gate Oxide Integrity Failure Structure Analysis Using Transmission Electron Microscopy

Author

Li, Y.G. ; Tan, S.H. ; Kuan, H.P. ; Tan, K.T. ; Duan, L.J.

Author_Institution

Syst. on Silicon Manuf. Co. Pte. Ltd., Singapore

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

2190

Lastpage

2192

Abstract

In this paper, cross-sectional TEM combined with plan-view TEM analysis was employed to investigate the gate oxide integrity (GOI) failure isolated using infrared optical beam induced resistance change (IR-OBIRCH) method. The cross-sectional TEM investigation only shows gate oxide breakdown and fused active under the spacer. However, plan-view TEM analysis reveals clearly the breakdown happened at the poly edge due to smaller spacer related to over etch of spacer nitride or oxide. EF-TEM elemental mapping shows Co migrates electrically to the fused active area

Keywords

CMOS integrated circuits; copper; electric breakdown; electromigration; failure analysis; transmission electron microscopy; CMOS gate oxide integrity; EF-TEM elemental mapping; IR-OBIRCH; cross-sectional TEM; failure structure analysis; gate oxide breakdown; infrared optical beam induced resistance change method; plan-view TEM analysis; transmission electron microscopy; Circuit faults; Cobalt; Electric breakdown; Failure analysis; Fault location; Optical beams; Semiconductor device manufacture; Semiconductor devices; Silicon; Transmission electron microscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306677

Filename

4098664