DocumentCode :
3474869
Title :
Associative memory with fully parallel nearest-manhattan-distance search for low-power real-time single-chip applications
Author :
Yano, Y. ; Koide, T. ; Mattausch, H.J.
Author_Institution :
Hiroshima University
fYear :
2004
fDate :
27-30 Jan. 2004
Firstpage :
543
Lastpage :
544
Abstract :
A fully-paralled minimum Manhattan-distance search associative memory has been designed in 0.35μm CMOS with 3-metal layers. The nearest-match unit consumes only 1.02mm2, while the chip area is 7.49mm2. The measured winner-search time of this chip, the time to determine the best-matching reference-data word for an input-data word among a database of 128 reference words (5-bit, 16 units), is < 180nsec. This corresponds to a performance requirement of 16 GOPS/mm2, if a 32-bit computer with the same chip area would have to run the same workload. Furthermore the power dissipation of the designed test chip is only about 26.7mW/mm2.
Keywords :
Analog-digital conversion; Associative memory; Circuit testing; Data compression; Electronic mail; Encoding; Gray-scale; Hardware; Pattern recognition; Power dissipation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Conference_Location :
Yohohama, Japan
Print_ISBN :
0-7803-8175-0
Type :
conf
DOI :
10.1109/ASPDAC.2004.1337640
Filename :
1337640
Link To Document :
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