Title :
A Fast-Locking Digital Phase-Locked Loop
Author :
Wagdy, Mahmoud Fawzy ; Vaishnava, Srishti
Author_Institution :
Dept. of Electr. Eng., California State Univ., Long Beach, CA
Abstract :
A conventional digital phase-locked loop (DPLL) is designed using (Baker et al., 2003) to operate at 1GHz using 0.18 mum CMOS technology; its lock time is 4.19 mus. By adding a coarse/fine tuning control unit composed of a digital-to-analog converter (DAC) and a counter as well as switching the currents of the charge pump, a fast-locking DPLL results, with a lock time of 1.02 mus, i.e. an improvement by a factor of 4. Simulations for both DPLLs verified the performance improvement due to using a fast-locking technique
Keywords :
counting circuits; digital phase locked loops; digital-analogue conversion; tuning; 0.18 micron; 1 GHz; 1.02 mus; 4.19 mus; CMOS technology; coarse tuning control; digital phase-locked loop; digital-to-analog converter; fine tuning control; CMOS technology; Charge pumps; Circuits; Clocks; Filters; Frequency synthesizers; Phase frequency detector; Phase locked loops; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Information Technology: New Generations, 2006. ITNG 2006. Third International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7695-2497-4
DOI :
10.1109/ITNG.2006.6
