Investigation of a low cost solder bumping technique for flip-chip interconnection

As the demand for flip-chip products increases, the need for high volume, low cost manufacturing processes also increases. All technology roadmaps point towards higher performance products based on finer pitch, high I/O count components. These requirements will push existing low cost solder bumping technologies to their practical limits and future products may have to use higher cost, lower throughput production strategies to achieve the requisite feature sizes. Currently, solder paste printing is the solder deposition method of choice for device pitches down to 150-200 μm; however, limitations in print quality and solder paste volume mean that this technology is not likely to move significantly below this pitch. The attractiveness of solder paste printing as a deposition technique due to its low cost and established infrastructure mean that methods for extending its application beyond 150 μm pitch would be desirable. This paper describes experiments conducted on carriers made from silicon for bumping of die using solder paste. An anisotropic etching process was used to generate pockets in the silicon surface into which solder paste was printed. Die were then placed against the carrier and reflowed to transfer the solder directly to the bond pads. An assessment was carried out of the potential application and limitations of this technique for device pitches at 225 and 127 μm. This was based on experimental observations and model calculations of the efficiency with which the Si carrier apertures could be filled with solder paste