A buffer planning algorithm with congestion optimization

This paper studies the problem of buffer planning for interconnect-centric floorplanning. We dense a congestiondriven buffer insertion algorithm, in which single-pair shortest-path model is used to compute optimal buffer locations and simultaneously to preserve the monotonicity of routing paths. Congestion estimation is achieved by an approach of probabilistic analysis. In order to get more buffers inserted, on the basis of a rough estimation of buiTer locations, some channels determined by the boundaries of circuit block are inserted, while the topology of the placement ´ keeps unchanged. Furthermore, we change the distribution of the dead space among blocks to optimize the time closure and routing congestion. The performance of the chip can he improved greatly on penalty of a small area usage. The effectiveness of the proposed algorithm has been demonstrated by the experimental results.