Specialty Memories - Performance Through Architecture

The emergence of new, high-speed RISC and CISC CPUs and high-performance communications channels impose ever increasing requirements on memory subsystems. Clock frequencies are reaching and exceeding 5OMHz, and memory transfers which must be performed in a single clock cycle demand matching performance from the memory subsystems. Specialty memory devices derive their high performance from their architecture as well as from their underlying technology. Architectural innovation provides enhancements that match the performance gained by moving one or more generations of 10 lithography. Examples of such innovations are many: burst mode logic on memory chips allow single cycle transfers in cache memory refill operations; on-chip address latch saves propagation delays for MIPS3000 and 386 cache subsystems, self-timed static RAMs accelerate ECL memory subsystems, etc. This paper concentrates on the system level performance gained by changing the interface style in RAMs and FIFOs.