• DocumentCode
    3475367
  • Title

    Buffer allocation algorithm with consideration of routing congestion

  • Author

    Yuchun Ma ; Xianiong Hong ; Sheqin Dong ; Song Chen ; Yici Cai ; Chung-Kuan Cheng ; Jun Gu

  • Author_Institution
    Tsinghua University
  • fYear
    2004
  • fDate
    27-30 Jan. 2004
  • Firstpage
    621
  • Lastpage
    623
  • Abstract
    The dominating contribution of interconnect to system performance has made it critical to plan the buffers and the routes resource in the early stage of the layout. In this paper, we present a congestion estimation model which takes the buffer insertion sites into consideration. Based on the feasible region of the buffer insertion, the two-level tile structure is used to represent the distribution of the feasible buffer insertion sites among the routing tiles. And the buffer allocation method is pertormed based on the congestion estimation, which can find the buffer locations with good congestion result. Our approach can be embedded into the floorplanning process and the experimental results show the efficiency of our method.
  • Keywords
    Computer science; Delay; Integrated circuit interconnections; Optimization methods; Routing; System performance; Tiles; Timing; Transistors; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
  • Conference_Location
    Yohohama, Japan
  • Print_ISBN
    0-7803-8175-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2004.1337666
  • Filename
    1337666