Abstract :
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one of the most effective and popular techniques to reduce interconnnect delay and decouple coupling effects. It is traditionally applied to post-layout optimization. However, it is obviously infeasible to insert hundreds of thousands buffers during the post-layout starge when most routing regions are occupied. Therefore, it is desirable to incorporate buffer planning into floor-planning to ensure thiming closure and design convergence. In this paper, we drive the formulae of feasible regions, and integrate buffer planning with floor-planning to optimize area, timing, noise, and congestion (routability) simultaneously. In particular, we treat each buffer block as a soft module and apply Lagragian relaxation to optimize the floorplan area. Experimental results show that our method obtains an average suceess rate of 94.9% (86.4%) of nets meeting timimg constraint alone (both timing and noise constraints)and consumes an average extra area of only 0.1% (0.2%) over the given floorplan.
