Title :
Verification of timed circuits with symbolic delays
Author :
Clariso, Robert ; Cortadella, J.
Author_Institution :
Universitat Politecnica de Catalunya
Abstract :
Verifying timed circuits is a complex problem even when the delays of the system are fixed. This paper deals with a more challenging problem, the formal verification of timed circuits with unspecified delays represented as symbols. The approach discovers a set of sufficient linear constraints on the symbols that guarantee the correctness of the circuit. Experimental results from the area of asynchronous circuits show the applicability of the approach.
Keywords :
Asynchronous circuits; Automatic testing; Clocks; Delay systems; Feedback; Flip-flops; Formal verification; Information analysis; Timing; Wires;
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Conference_Location :
Yohohama, Japan
Print_ISBN :
0-7803-8175-0
DOI :
10.1109/ASPDAC.2004.1337668
