Title :
Parallel verilog simulation: architecture and circuit partition
Author :
Tun Li ; Yang Guo ; Sikun Li ; FuJiang Ao ; GongJie Liu
Author_Institution :
National University of Defense Technology
Abstract :
This paper presents parallel VerUog simulation architecture bases on optimistic asynchronous pardel simulation algorithm and MPI library, and proposes a novel emclent modnbbased partition algorithm combined with pre-slmulation partition algorithm. Wlth the presented architecture and partition algorithm, parallel VerUog simulation can get promising speedup, as well as distdbuted workload and communication cost across processors.
Keywords :
Algorithm design and analysis; Circuit simulation; Costs; Digital systems; Hardware design languages; Kernel; Libraries; Partitioning algorithms; Time warp simulation; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Conference_Location :
Yohohama, Japan
Print_ISBN :
0-7803-8175-0
DOI :
10.1109/ASPDAC.2004.1337671
