DocumentCode
3475624
Title
Accurate and eff icient flow based congestion estimation in floorplanning
Author
Zion Cien Shen ; Chu, C.C.N.
Author_Institution
Iowa State University
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
671
Lastpage
676
Abstract
Congestion has been a topic of great importance in the floorplanning of deep-submicron Odesign. In this paper, we design an accurate and efficient congestion estimation model by performing global routing. We interpret the global routing problem as a flow problem of several commodities and relax the integral flow constraints. The objective of resulting fractional flow problem is to minimize the maximum congestion over all edges in the inner dual graph [ 131. The underlying routing graph for each commodity is derived by assigning directions to the inner dual graph edges. We design an efficient two-phase algorithm to solve this fractional flow problem. The first phase is denoted as Incoming Flow Balancing (IFB) by which a good initial solution is derived. The second phase is called Srepwise Flow Refinement (SFR) by which the maximum congestion of the solution in first phase is iteratively reduced to its optimal value. In addition, a valid global routing solution can be obtained by applying a simple rounding procedure on the fractional flow solution. The maximum congestion after rounding is only increased by 2.82% on average according to our experimental results. which justifies the use of fractional flow to estimate the routing congestion. Finally. we demonstrate our model by integrating it into a simulated annealing (SA) based floorplanner, where we use the maximum congestion as part of the cost of SA. The experimental results show that, on average, our congestion-driven floorplanner can generate a much less congested floorplan (-36.44%) with a slight sacrifice in area (+1.30%) and wirelength (+2.64%). The runtime of the whole SA process is only increased moderately (+270%).
Keywords
Costs; Design optimization; Integrated circuit interconnections; Process design; Routing; Runtime; Shape; Simulated annealing; State estimation; Tiles;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Conference_Location
Yohohama, Japan
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337677
Filename
1337677
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