Systolic array based processing for linear multivariable feedback control schemes

Candidate array architectures for the implementation of multivariable systems are developed. Following preliminary development of a SIMD architecture, the dual look-ahead approach is introduced in order to reduce the processing delay associated with M-expanded pipelining. Macro-systolic architectures mapped from this are also given. Both word-level and lower-level pipelining have been studied under the constraint of retaining a short and system-order-independent latency. Trade-offs exist in all of these architectures. These architectures can also be mapped onto coarse-grain architectures, such as those based on transputers, with each realizing a matrix-vector multiplier or a systolic cell