A mixed-mode extraction flow for high performance microprocessors

This paper describes a mixed mode chip level extraction flow deployed in high performance micropmessor designs. Two extracton of different accuracy levels are integrated to achieve hest trade-off between run-time and precision. The goal is to provide suRicient accuracy at different design stages and achieve minimum extraction time possible. Three different extraction modes are made available through combination of an in-house 2D extractor and a vendor 3D extractor: 2D estimated, 2D actual and 3D extraction. The applications in real design projects showed around 75% extraction time-savings hy combining these three modes together with a guarantee on meeting timing closure at the end.