Title :
A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC
Author :
Yi-Cheng Chen ; Jyun-Syong Lai ; Zhi-Ming Lin
Author_Institution :
Integrated Circuit Design of Comput. Sci. & Inf. Eng., Nat. Changhua Univ. of Educ., Changhua, Taiwan
Abstract :
In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-μm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/-0.23 LSB differential non-linearity error (DNL) and +0.24/-0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); encoding; sample and hold circuits; TSMC CMOS process; analog-to-digital converter; binary code encoder; differential nonlinearity error; integral nonlinearity; interpolating circuit; power 0.73 mW; power dissipation; sample-and-hold circuit; single-transistor comparators; size 0.18 mum; thermometer code; two-channel time interleaved interpolating flash ADC; voltage 1.5 V; word length 6 bit; ISO standards; Time-frequency analysis; Interpolation; analog-to-digital converter (ADC); comparator; flash adc;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of
Conference_Location :
Hong Kong
DOI :
10.1109/EDSSC.2013.6628099
