DocumentCode :
3475895
Title :
An SoC architecture and its design methodology using unifunctional heterogeneous processor array
Author :
Yuyama, Y. ; Aramoto, M. ; Kobayashi, K. ; Onodera, H.
Author_Institution :
Kyoto University
fYear :
2004
fDate :
27-30 Jan. 2004
Firstpage :
737
Lastpage :
742
Abstract :
We propose a heterogeneous processor architecture and its design methodology to shonen the design period of the SOC. It enables fast implementation of a system LSI including an embedded CPU and peripheral functional blocks. Each functional block of the system under design is implemented to a customized processor, instead of a peripheral hardwired logic. We customize processors by deleting unneccesarry funclionalities, without adding new features. This eables rapid and bug-free design. Although area, power and performance of the proposed architecture are a little bit inferior to those of hardwired logics, the design period of the processor is considerably minimized. since the ROM pattern (software) and the layout pattern (customized processor, i.e. hardware) can be independently designed in parallel.
Keywords :
Application specific processors; Computer architecture; Computer bugs; Design methodology; Hardware; Informatics; Large scale integration; Logic design; Read only memory; Software performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Conference_Location :
Yohohama, Japan
Print_ISBN :
0-7803-8175-0
Type :
conf
DOI :
10.1109/ASPDAC.2004.1337691
Filename :
1337691
Link To Document :
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