A high performance bus communication architecture through bus splitting

A split shared-bus nrcbitecture with multiple simultaneous bus accesses is proposed. Compared to traditional bus nrchitectures, the performance of proposed architechue is higher hecause of the ability to deliver multiple bus transsetions in one bus cyde. We also p r o w an implementation of the BP biter, which not only detects and grants multiple Compatible bus transactions, but also mnbols splitters properly to establish the communication paths for those transactions. Experimental results show that the hns architecture CM have up to 23 times improvement in the effective bandwidth and up to 5 times reduction in the communication latency. Moreover, the arbiter implementatiou has reasooahle nrea and timing cost, making it suitable for high performance SoC applications.