A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement

This paper presents a methodology which can substantially reduce the bus power consumption in memory dominated systems. It systematically combines an activity driven placement of the memories and a bus segmentation approach for the interconnect to localize the wire switching activity and minimize the associated wire capacitive load of the memory bus. A factor of 2.8 in bus power reduction is achieved for a real life design while maintaining the same performance.