A study using two stage NBTI model for 32 nm high-k PMOSFET

Author

Hussin, Husnayati ; Muhamad, Maizan ; Abdul Wahab, Y. ; Shahabuddin, S. ; Soin, Norhayati ; Bukhori, M.F.

Author_Institution

Fac. of Electr. Eng., Univ. Teknol. MARA, Shah Alam, Malaysia

fYear

2013

fDate

3-5 June 2013

Firstpage

1

Lastpage

2

Abstract

Kinetics of E´centers and threshold voltage shift, (ΔVth) of High-K Metal Gate Stacks has been comprehensively studied using two - stage Negative Bias Temperature Instability (NBTI) model. To effectively study the kinetics of E´ centers, the two stage model was simulated with stage one only and then simulated in both stages. The evolution of trap kinetics was further investigated by varying parametric of energy barriers. We found that the model capable to explain the hole trapping and de-trapping mechanism occurs in NBTI degradation particularly on the transformation between hole traps into a more permanent form which explain the process of de-passivation of interface trap precursor as triggered by hole captured at an E´ center precursor.

Keywords

MOSFET; high-k dielectric thin films; hole traps; negative bias temperature instability; E´centers precursor; high-k PMOSFET; high-k metal gate stacks; hole de-trapping mechanism; hole trapping mechanism; interface trap precursor depassivation; size 32 nm; threshold voltage shift; trap kinetics; two stage NBTI model; two-stage negative bias temperature instability model; Charge carrier processes; High K dielectric materials; MOSFET circuits; Metals; E´ Centers; High-k PMOSFET; Hole trapping and de-trapping; NBTI; Two stage model; Vth Degradation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of

Conference_Location

Hong Kong

Type

conf

DOI

10.1109/EDSSC.2013.6628108

Filename

6628108