Parametric reduced order modeling for interconnect analysis

VLSI circuit models are subject to parameter variations due to temperature, geometry, process, and operating conditions. Parameter model order reduction is motivated by such practical problems. The purpose is to obtain a parametric reduced order model so that repeated reduction can be avoided. In this paper we propose two techniques: a nominal projection technique and an interpolation technique. The nominal projection technique is effective for small parameter perturbation by using a robust projection. The interpolation technique takes the advantage of simple matrix structure resulting from the PVL algorithm. A new moment matching concept in the discrete-time domain is also introduced, which is intended for a better performance in waveform matching and stability. Interconnect examples are used to test the effectiveness of the proposed methods.