DocumentCode :
3476057
Title :
Capacitive dynamic comparator with low kickback noise for pipeline ADC
Author :
Ko-Chi Kuo ; Chi-Wei Wu
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan
fYear :
2013
fDate :
3-5 June 2013
Firstpage :
1
Lastpage :
2
Abstract :
A kickback noise capacitive dynamic comparator is presented. The low kickback noise is achieved by controlling additional MOSFETs in signal path to cancel voltage variation in the internal node of comparator. A neutralization technique is also implemented into the proposed design to further reduce the impact of kickback noise in the inputs of comparator. By adapting both techniques, the kickback noise of the proposed dynamic comparator is reduced 23 times smaller compared to that of conventional implementation at 500mV differential input voltage and 250MHz operating speed. The design is implemented in TSMC 0.18-μm CMOS technology process with 1.8V power supply and consumes 44.5μw power dissipation.
Keywords :
CMOS integrated circuits; MOSFET; analogue-digital conversion; comparators (circuits); pipeline processing; power supplies to apparatus; semiconductor device noise; MOSFET control; TSMC CMOS technology process; comparator internal node; differential input voltage; frequency 250 MHz; kickback noise capacitive dynamic comparator; neutralization technique; pipeline ADC; power 44.5 muW; power dissipation; power supply; size 0.18 mum; voltage 1.8 V; voltage 500 mV; voltage variation; Switches; ADC; Comparator; Kickback noise;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of
Conference_Location :
Hong Kong
Type :
conf
DOI :
10.1109/EDSSC.2013.6628111
Filename :
6628111
Link To Document :
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