Wafer Reliability Evaluation and Monitoring for InGaAsP Devices

Author

Verbitsky, David E.

Author_Institution

Alefa-EEQRA, Edison, NJ

fYear

2006

fDate

Oct. 16 2006-Sept. 19 2006

Firstpage

201

Lastpage

204

Abstract

A simple procedure, evaluating wafer reliability by HALT before full regular processing, is justified and optimized. This procedure is aimed at early failure rate assessment, reliability adjustment, and yield enhancement per customer needs. A test plan concept, detailed design and realization are suggested. Test optimization with respect to customer requirements, field failures, and manufacturing losses are presented. Some regular flaws and recommendations are proposed. The procedure allows significant manufacturing and field savings along with increasing customer satisfaction. The procedure can be extended to manufacturing operation optimization and applied to related GaAs and Si based innovative technologies

Keywords

III-V semiconductors; gallium arsenide; indium compounds; semiconductor device manufacture; semiconductor device reliability; InGaAsP; early failure rate assessment; manufacturing operation optimization; reliability adjustment; wafer reliability evaluation; yield enhancement; Application software; Cable TV; Communication cables; Computer network reliability; Customer satisfaction; Failure analysis; Investments; Life testing; Manufacturing; Monitoring;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2006 IEEE International

Conference_Location

South Lake Tahoe, CA

ISSN

1930-8841

Print_ISBN

1-4244-0296-4

Electronic_ISBN

1930-8841

Type

conf

DOI

10.1109/IRWS.2006.305246

Filename

4098723