High speed test structures for in-line process of 3D system in packaging

As the requirement of portable and smart devices rapidly increasing, applications of high performance 3D integration and M/NEMS packaging have enormous market potential. High speed in-line testing is a critical bottleneck for 3D SiP and TSV processes. In this paper, we promote a method of in-line testing for interconnection performance of TSV structures, and a novel 3D CPW model for performance testing is introduced. The S parameters and Z parameters are simulated respectively. To determine the optimum TSV diameter and sidewall thickness, different types of the model have been analyzed. During our experiments, a typical structure for high frequency performance testing was fabricated successfully. The results were compared with related simulations. By using this method, the high frequency performance testing of TSV can be achieved.