Minimization of the expected path length in BDDs based on local changes

In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can he crucial and is measured by the expected path length of the BDD. In this paper a new technique for BDD minimization with respect to the expected path length is suggested to reduce evaluation time. It is based on sifling and, unlike previous approaches, performs variable swaps with the same time complexity as the original sifting algorithm. Another field of application for BDDs is logic synthesis, often targeting Pass Transistor Logic (PTL) because of low power and low cost. A minimization of BDD size and chip area can lead to poor timing performances. We suggest to also use our method here, as the resulting BDDs show a very low maximal and average path delay. This supports the synthesis of high-speed PTL circuits at low area overhead. Experimental results are given to show the efficiency of our approach.