Flip chip assembly with advanced RDL technology

With silicon node technology shrinking to beyond 14nm, die pad pitch becomes smaller and bumps become finer dimensioned so that I/O pads can be laid out. In many cases, flip chip assembly is required because of layout considerations, performance, and cost effectiveness. Often, the fine pitch layout poses great challenges to existing bumping and flip chip assembly capability. This paper is to report an advanced redistribution layer (RDL) solution for a tighter pitch designed die so that that current flip chip assembly process can be used. The test vehicle die has two rows of staggered 40/80um pitch peripheral pads. The RDL is constructed with PBO-Cu-PBO stack and an advanced 10/10um L/S RDL design rule. After the RDL application, the bump pitch of the die is expanded into an area array flip chip type with 170um pitch. Mechanical, Electrical, Constructional analysis is reported in the paper. Assembly process and manufacturability with thermal compression flip chip technology is evaluated. Initial construction analysis and reliability test is conducted. The results clearly show that this RDL technology is feasible and potentially a viable choice for new Silicon node technology die with tight pitch.