On achieving complete coverage of delay faults in full scan circuits using locally available lines

We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modifications to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and performance overheads. The proposed technique allows us to achieve complete coverage of detectable delay faults. A simple test generation procedure that guarantees complete coverage when used with the proposed technique is also described