Title :
Port interference faults in two-port memories
Author :
Hamdioui, Said ; van de Goor, A.J.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
A two-port memory contains two similar ports, which can be accessed separately and independent of each other. In this paper, logical fault models are derived for the effect of shorts between the ports. The result is a set of new fault models, based on circuit simulation, together with a new test
Keywords :
CMOS memory circuits; SRAM chips; built-in self test; fault simulation; integrated circuit testing; logic testing; two-port networks; CMOS SRAM; circuit simulation; fault coverage; logical fault models; port interference faults; shorts between ports; state coupling fault; stuck open fault; test length; two-port SRAM; two-port memories; weak faults; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Computer architecture; Educational institutions; Electronic mail; Information technology; Interference;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805833
