A multi-scale framework for nano-electronic devices modeling with application to the junctionless transistor

In this paper we present a new multi-scale simulation scheme for next-generation electronic design automation (EDA) for nano-electronics. The scheme features a combination of the first-principles quantum mechanical calculation, semi-classical semiconductor device simulation, compact model generation and circuit simulation. To demonstrate the feasibility of the proposed scheme, we apply our newly developed quantum mechanics/electromagnetics method to simulate the junctionless (JL) transistors. Based on the calculated I-V curves, a compact model is then constructed for the JL transistors. The validity of the compact model is further verified by the transient circuit simulation of an inverter.