DocumentCode :
3476735
Title :
A unified model for timing speculation: Evaluating the impact of technology scaling, CMOS design style, and fault recovery mechanism
Author :
De Kruijf, Marc ; Nomura, Shuou ; Sankaralingam, Karthikeyan
Author_Institution :
Vertical Res. Group, Univ. of Wisconsin - Madison, Madison, WI, USA
fYear :
2010
fDate :
June 28 2010-July 1 2010
Firstpage :
487
Lastpage :
496
Abstract :
Due to fundamental device properties, energy efficiency from CMOS scaling is showing diminishing improvements. To overcome the energy efficiency challenges, timing speculation has been proposed to optimize for common-case timing conditions, with errors occurring under worst-case conditions detected and corrected in hardware. Although various timing speculation techniques have been proposed, no general framework exists for reasoning about the trade-offs and high-level design considerations of timing speculation. This paper develops two models to study the end-to-end behavior of timing speculation: a hardware-level efficiency model that considers the effects of process variations on path delays, and a complementary system-level recovery model. When combined, the models are used to assess the impact of technology scaling, CMOS design style, and fault recovery mechanism on the efficiency of timing speculation. Our results show that (1) efficiency gains from timing speculation do not improve as technology scales, (2) ultra-low power (sub-threshold) CMOS designs benefit most from timing speculation - we report a 47% potential energy-delay reduction, and (3) fine-grained fault recovery is key to significant energy improvements. The combined model uses only high-level inputs to derive quantitative energy efficiency benefits without any need for detailed simulation, making it a potentially useful tool for hardware developers.
Keywords :
CMOS logic circuits; circuit reliability; logic design; CMOS design; common case timing condition; energy delay reduction; fault recovery mechanism; fine grained fault recovery; timing speculation; CMOS technology; Circuit faults; Energy efficiency; Error analysis; Error correction; Hardware; Mechanical factors; Power system modeling; Semiconductor device modeling; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Dependable Systems and Networks (DSN), 2010 IEEE/IFIP International Conference on
Conference_Location :
Chicago, IL
Print_ISBN :
978-1-4244-7500-1
Electronic_ISBN :
978-1-4244-7499-8
Type :
conf
DOI :
10.1109/DSN.2010.5544278
Filename :
5544278
Link To Document :
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