Cu-Sn low-temperature stack bonding for 3D packaging

In this paper, a three-dimensional (3D) chip bonding technology using Cu-Sn solder was described. First of all, the interdiffusion process of elemental Cu and Sn in the bonding region was discussed, and some key factors were identified to influence the performances of bonding layer: temperature, pressure, atmosphere and annealing time. Scanning electron microscopy (SEM) and optical microscopy were used to study the morphology of the bonding layer in solder joints before and after annealing. Then, bonding experiments were carried out to determine the optimal parameters of the Cu-Sn bonding, and 3D stacking bonding with TSV (Through Silicon Via) and Cu-Sn microbunmps was finished. Finally, the strength of bonded layers was characterized by shear testing and tensile testing, and the electrical and thermal properties of bonded layers were tested. All the results have been compared with that of Cu-Cu thermal compression bonding.