A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture

Author

Sachan, Ruchi ; Ali, Shady ; Bist, C. ; Misra, Sudip ; Menezes, V. ; Gupta, Swastik ; Bosshart, P.

Author_Institution

Technol. & Manuf. Gro Texas Instrum. India Ltd., Bangalore, India

fYear

2013

fDate

5-10 Jan. 2013

Firstpage

55

Lastpage

59

Abstract

Ternary content addressable memory (TCAM) is used for high-speed table lookups. The dynamic power consumption of TCAMs is one of the main challenges for keeping up with high performance requirements. System level reliability is impacted by devices that produces large peak current demands on the power grid. This paper presents a TCAM compiler based on a static complementary TCAM bitcell for reduced dynamic power and reduced decoupling capacitance(dcap) requirement. The two stage architecture comprise of static TCAM cells with a match forward feature and then a static AND-tree structure. This TCAM compiler configurations have been implemented on 40nm CMOS technology testchip and experimental results demonstrate the performance upto 650Mhz and 0.5fJ/bit/search energy for a 512wordsx256bit macro.

Keywords

CMOS memory circuits; content-addressable storage; table lookup; CMOS technology testchip; TCAM compiler; complementary bit-cell architecture; dynamic power consumption; frequency 650 MHz; power grid; size 40 nm; static AND-tree structure; static complementary TCAM bitcell; system level reliability; table lookup; ternary content addressable memory; Associative memory; Clocks; Computer architecture; Impedance matching; Layout; Power demand; Power system dynamics; TCAM; memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on

Conference_Location

Pune

ISSN

1063-9667

Print_ISBN

978-1-4673-4639-9

Type

conf

DOI

10.1109/VLSID.2013.162

Filename

6472613