DocumentCode :
3476869
Title :
A 3-transistor CMOS active pixel with in-pixel correlated double sampling
Author :
Shaohua Liu ; Lai Jiang ; Yu Hang ; Yan Li ; Dao ming xi ; Qingguo Xie
Author_Institution :
Shenzhen City Key Lab. of Embedded Syst. Design, Shenzhen Univ., Shenzhen, China
fYear :
2013
fDate :
3-5 June 2013
Firstpage :
1
Lastpage :
2
Abstract :
This paper presents a 3-transistor CMOS active pixel structure with in-pixel correlated double sampling. Designed in a standard 0.18 μm CMOS process, the structure effectively suppresses temporal noise and fixed pattern noise (FPN), thanks to the shared correlated double sampling circuit inside the pixel. Fill factor is also improved while maintaining pixel performance. Validation by Spectre simulator shows that the proposed structure suppresses 100 mV input offset to the microvolt range, and the pixel readout time is ~90 ns. The average power consumption of each pixel is 18 μW.
Keywords :
CMOS image sensors; correlation theory; integrated circuit noise; interference suppression; transistor circuits; CMOS process; FPN suppression; Spectre simulator; fill factor; fixed pattern noise; in-pixel correlated double sampling circuit; power 18 muW; size 0.18 mum; temporal noise suppression; transistor CMOS active pixel structure; CMOS integrated circuits; CMOS active pixel; correlated double sampling; shared pixel structure;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of
Conference_Location :
Hong Kong
Type :
conf
DOI :
10.1109/EDSSC.2013.6628152
Filename :
6628152
Link To Document :
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