Investigation of ultra-thin BOX junctionless transistor at channel length of 20 nm

Silicon-on-insulator junctionless transistor (SOI-JLT) have been considered a promising candidate to extend planer CMOS scaling. This technology allows significant improvement of the transistors electrostatic control and variability below 20 nm regime. This paper presents ultra-thin back oxide (BOX) SOI-JLT device with gate length of 20 nm. We reported that thin BOX is effective in adjusting threshold voltage (V_th) by means of BOX thickness scaling and substrate doping concentration. Its characteristics like I_ON/I_OFF, DIBL and subthreshold slope are investigated in detail as BOX thickness varied from 5 nm to 50 nm with substrate doping variation from 10¹⁶ cm^-3 to 10¹⁹ cm^-3. The simulation results show I_ON/I_OFF ratio improved by factor 1.2 × 10⁴ (NJLT) and 6 × 10³ (PJLT) with BOX thickness scaling from 50 nm to 5 nm at substrate doping 1019 cm^-3. Threshold voltage is increased by 427 mV (NJLT) and 421 mV (PJLT), while DIBL variation is reduced by 71 mV=V (NJLT) and 83 mV=V (PJLT) with less than 5% variation in subthreshold swing for both NJLT and PJLT. An inverter circuit is designed and simulated based on the concept of ultra thin BOX junctionless transistor. The transistor operation is in accumulation mode, different from the conventional CMOS devices with inversion mode of operation. Simulations results show good DC and transient characteristics for gate length of 20 nm and 10 nm at V_dd = 0.9 V.