Title :
Characteristics of gate inside junctionless transistor with channel length and doping concentration
Author :
Kumar, Pranaw ; Sahu, Chitrakant ; Shrivastava, Ashish ; Kondekar, P.N. ; Singh, Jaskirat
Author_Institution :
Dept. of Electron. & Commun. Eng., PDPM IIITDM, Jabalpur, India
Abstract :
A novel device structure has been proposed in this paper for junctionless transistor with gate inside device architecture. Its characteristics are demonstrated at gate length of 30 nm. The proposed device shows very good ION/IOFF ratio approximately 108, excellent sub-threshold swing (SS) 63 mV=dec, improved drain induced barrier lowering (DIBL) 40 mV with high ON-state current and extremely low leakage current. The various device parameters are also observed for channel length of 22 nm and 14 nm. The device shows improved short-channel effects with no junction between channel and source/drain, which greatly simplifies the fabrication process at nano scale level. A 3-D ATLAS numerical simulation has been carried out for the proposed device structure.
Keywords :
MOSFET; doping profiles; leakage currents; 3-D ATLAS numerical simulation; ION/IOFF ratio; channel length; doping concentration; drain induced barrier lowering; gate inside junctionless transistor; high ON-state current; leakage current; short-channel effects; size 14 nm to 30 nm; sub-threshold swing; Doping; Electronic mail; Junctions; Logic gates; Numerical models; Semiconductor process modeling; Transistors;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of
Conference_Location :
Hong Kong
DOI :
10.1109/EDSSC.2013.6628156
