VLSI Implementation of Enhanced Edge Preserving Impulse Noise Removal Technique

In many applications, image and video signals are corrupted by impulse noise during acquisition or transmission. Hence there is a need for an efficient and consumer friendly impulse noise removal technique. In this paper, an efficient low cost VLSI architecture for the edge preserving impulse noise removal technique has been proposed. The architecture comprises of two line buffers, register banks, impulse noise detector, edge oriented noise filter and impulse arbiter. The storage space required for the proposed hardware is two line buffer rather than full frame memory. Moreover, proposed algorithm involves only fixed size window instead of variable window size. These two greatly reduces storage requirement as well as computation complexity. The impulse noise detector turns off the remaining circuitry if the current pixel is noise free, thus reducing power consumption. Further, the four stage pipeline architecture greatly improves the speed of operation. The implemented edge preserving algorithm results in better visual quality for denoised image. Thus the proposed architecture has less complexity, less storage requirement, low power consumption and improved speed of operation. The architecture has been implemented in Xilinx 9.2i and the results are tabulated for various images.