DocumentCode
3477248
Title
Gate-drain capacitance behaviour of the DMOS power transistor under high current flow
Author
Deml, C. ; Hoffmann, K.
Author_Institution
Siemens AG, Munich, Germany
Volume
2
fYear
1998
fDate
22-22 May 1998
Firstpage
1716
Abstract
The gate-drain capacitance of a power DMOS transistor was measured under high current conditions of up to 250 A. Depending on V/sub GS/ a strong nonlinear characteristic was observed. Using the measured capacitance data the characteristics of the inner MOS transistor and the epi region have been determined separately for parameterisation and modelling.
Keywords
capacitance; capacitance measurement; power MOSFET; semiconductor device models; DMOS power transistor; epi region; gate-drain capacitance behaviour; high current conditions; high current flow; inner MOS transistor; measured capacitance data; modelling; nonlinear characteristic; parameterisation; Capacitance measurement; Capacitance-voltage characteristics; Circuits; Current measurement; Equations; Fluid flow measurement; Power measurement; Power transistors; Thermal loading; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Electronics Specialists Conference, 1998. PESC 98 Record. 29th Annual IEEE
Conference_Location
Fukuoka
ISSN
0275-9306
Print_ISBN
0-7803-4489-8
Type
conf
DOI
10.1109/PESC.1998.703412
Filename
703412
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