Optoelectronic component, integration and packaging technology advancements, and their impact on massively parallel interconnects

The Honeywell Technology Center is developing an integrated optical interconnect fabric consisting of a variety of device, integration and packaging technologies designed to address massively parallel interconnects within backplanes and from chip to chip. For these interconnects comprising distances of 10 meters or less, the focus is upon reducing costs by increasing the levels of integration while still achieving high yields, utilizing low cost CMOS circuits whenever possible, developing reliable, robust, low power dissipation optoelectronic devices, and robust scalable interconnection systems. The initial chassis to chassis through a fiber array cable, or connect board to board through the use of fibers laminated to the board. Subsequently, chip to chip optical interconnects can further improve connectivity from chip to chip by implementing “smart pixel array” (SPA) technology. SPA modules integrate two dimensional (2D) arrays of optoelectronic device (VCSELs and photodetectors), silicon based electronic processing, drive and receive circuitry, and the passive optics required to condition and route the input and output optical beams