Title :
Assembly process simulation of TSV interposer
Author :
Chen Si ; Qin Fei ; Xia Guofeng ; Wu Wei ; Yu Daquan ; Lu Yuan
Author_Institution :
Coll. of Mech. Eng. & Appl. Electron., Beijing Univ. of Technol., Beijing, China
Abstract :
TSV interposer packaging is one of the most important applications for TSV technology. However, the warpage and residual stress arising from the assembly process of TSV interposer have important influence on the reliability of the package. In this paper, two assembly processes were simulated by using the Finite Element Method, the evolution of the stresses and warpage during assembly were compared to obtain the better process flow. According to the chosen process flow, the reliability of micro bumps during assembly was discussed, it was confirmed that both the structure deformation (including deformation of chip and interposer) and TSV-Cu protrusion have effects on the micro bump reliability, it´s necessary to take the relative orientation of the micro bumps, TSVs and underfill fillet into consideration during packaging designation.
Keywords :
assembling; finite element analysis; integrated circuit modelling; integrated circuit packaging; integrated circuit reliability; three-dimensional integrated circuits; TSV interposer packaging; TSV technology; TSV-Cu protrusion; assembly process simulation; finite element method; microbump reliability; package reliability; packaging designation; process flow; residual stress; structure deformation; underfill fillet; Finite element analysis; Reliability; Soldering; Strain; Stress; Through-silicon vias; TSV interposer; micro bump; numerical simulation; process flow; warpage;
Conference_Titel :
Electronic Packaging Technology (ICEPT), 2013 14th International Conference on
Conference_Location :
Dalian
DOI :
10.1109/ICEPT.2013.6756461