Title :
An ADEPT performance model of the Mercury RACEway crossbar interconnection network
Author :
Han, Gang ; Aylor, James H. ; Klenke, Robert H.
Author_Institution :
Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
Abstract :
The Naval Research Lab (NRL) has developed a graphical notation called the Processing Graph Method (PGM) and a set of tools to implement the PGM environment called PGM Tools (PGMT). A major capability currently missing from PGMT is to receive feedback on the performance of the algorithm and scheduler on a specific architecture without actually executing the algorithm on that architecture with real data. The parallel computing architecture used in NRL is the i860 based Mercury RACE Multi-computer. The RACEway interconnection network is a hierarchical crossbar-based network which supports concurrent, priority-based, preemptable data transfer between system nodes. This paper outlines a performance modeling methodology based on the UVa ADEPT VHDL-based performance modeling environment. A simulation model for the RACEway crossbar interconnection network is presented to evaluate the performance of the network with respect to the traffic load on it. The integrated architecture/algorithm/scheduler model also provides an efficient way to evaluate the application algorithms and scheduling strategies on a specific multi-computer system
Keywords :
digital simulation; hardware description languages; hierarchical systems; multiprocessor interconnection networks; parallel architectures; performance evaluation; signal processing; ADEPT performance model; DSP algorithms; Mercury RACEway crossbar interconnection network; Naval Research Lab; PGM Tools; PGM environment; Processing Graph Method; UVa ADEPT VHDL-based performance modeling environment; application algorithms; concurrent priority-based preemptable data transfer; graphical notation; hierarchical crossbar-based network; i860 based Mercury RACE multi-computer; integrated architecture/algorithm/scheduler model; network performance evaluation; parallel computing architecture; performance modeling methodology; scheduling strategies; simulation model; traffic load; Computer architecture; Digital signal processing; Feedback; Multiprocessor interconnection networks; Parallel processing; Processor scheduling; Scheduling algorithm; Signal processing algorithms; Switches; Telecommunication traffic;
Conference_Titel :
Parallel Interconnects, 1999. (PI '99) Proceedings. The 6th International Conference on
Conference_Location :
Anchorage, AK
Print_ISBN :
0-7695-0440-X
DOI :
10.1109/PI.1999.806398