• DocumentCode
    3477533
  • Title

    The process and stress-induced variability issues of trigate CMOS devices

  • Author

    Chung, Steve S.

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    2013
  • fDate
    3-5 June 2013
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Not only the popular random dopant fluctuation (RDF), but also the traps, caused by the hot carrier stress induce the Vth variations. This paper will address the importance of these effects and the experimental demonstration of the process- and trap-induced fluctuations. The boron clustering, sidewall roughness, and the electrical stress effects can all be justified by the theory and the method. This method provides us a valuable tool for the understanding of the process and stress induced variability in 3D devices (e.g., FinFET).
  • Keywords
    CMOS integrated circuits; MOSFET; fluctuations; semiconductor device reliability; stress effects; 3D devices; boron clustering; electrical stress effects; finFET; hot carrier stress; sidewall roughness; stress-induced variability; trap-induced fluctuations; trigate CMOS devices; Irrigation; Logic gates; MOSFET circuits; Stress; Reliability; Trigate CMOS; Variability; Variation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of
  • Conference_Location
    Hong Kong
  • Type

    conf

  • DOI
    10.1109/EDSSC.2013.6628181
  • Filename
    6628181
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3477533