Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators

This paper presents a two-path design of quadrature band-pass ΣΔ modulators and discusses the architectural level implementation issues for power reduction. The methodology uses an architecture which locks IF frequencies to the sampling frequency. The basic delay based solution is converted into integrator based solution for the implementation. Robustness of the structure against the mismatch is analyzed and a two-path quadrature cascaded modulator is proposed to alleviate signal band gain error tone. Simulations at the behavioral level verify the architecture implementation and the effectiveness of the approach.