DocumentCode :
3477586
Title :
A design of 13dBm IIP3 DVB-S.2 RF receiver with auto calibration technique
Author :
Na, Yoosam ; Yoo, Hyunhwan ; Kim, Moonsun ; Hwang, Hyeonseok ; Jo, Byeonghak
Author_Institution :
UC Bus. Team (Circuit design group), Samsung Electro-Mech., Suwon
fYear :
2008
fDate :
16-20 Dec. 2008
Firstpage :
1
Lastpage :
4
Abstract :
In this paper a full integrated CMOS single chip DCR DBS is presented. The receiver covered 0.95 GHz to 2.15 GHz broadband frequency. It contains an automatically gain controlled RF front-end including LNA, RFVGA, WBD/RSSI and proposed automatically fine controlled VCO band a role in good phase noise optimization with Fractional-N PLL. A fully programmable channel select filter effectively eliminates out of channel jammers. The proposed receiver shows a remarkable linearity performance 13 dBm of IIP3 at the minimum gain and wide dynamic range is over 80 dB. The high linearity, good phase noise and wide dynamic gain performance at low power consumption make it well suitable to the DVB-S2 application.
Keywords :
CMOS integrated circuits; automatic gain control; digital video broadcasting; low noise amplifiers; phase locked loops; IIP3 DVB-S.2 RF receiver; LNA; RFVGA; VCO; WBD-RSSI; auto calibration technique; automatic gain control; direct conversion receiver; fractional-N PLL; frequency 0.9 GHz to 2.15 GHz; full integrated CMOS single chip DCR DBS; phase noise optimization; Automatic control; Calibration; Digital video broadcasting; Linearity; Performance gain; Phase locked loops; Phase noise; Radio frequency; Satellite broadcasting; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microwave Conference, 2008. APMC 2008. Asia-Pacific
Conference_Location :
Macau
Print_ISBN :
978-1-4244-2641-6
Electronic_ISBN :
978-1-4244-2642-3
Type :
conf
DOI :
10.1109/APMC.2008.4957884
Filename :
4957884
Link To Document :
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