A low jitter digital phase-locked loop with a hybrid analog/digital PI control

This paper presents a novel digital phase-locked loop (DPLL) architecture with a hybrid analog/digital proportional/integral (PI) control to generate a low jitter output clock. The hybrid analog/digital PI control mitigates a time to digital converter (TDC) quantization noise and reduces the deterministic jitter (DJ). In addition, a digital phase accumulator (DPA) based high resolution digitally controlled oscillator (DCO) suppresses a DCO quantization error. To reduce a random jitter (RJ), we propose a closed loop voltage controlled oscillator (CLVCO) which can suppress the random noise of oscillator because of a negative feedback loop. We design the proposed DPLL architecture in 130 nm CMOS technology at 1.2V supply. The proposed low jitter DPLL shows 4.3 psec of the DJ and 12.5 psec of the RJ. This DPLL operates from 256 MHz to 1.024 GHz and consumes 4.1 mW at 1.024 GHz output frequency.