DocumentCode
3477739
Title
Impact of Power Supply Noise on Clock Jitter in High-Speed DDR Memory Interfaces
Author
Monthie, J. ; Sreekumar, V. ; Yashwante, R.
Author_Institution
LSI, Inc., Milpitas, CA, USA
fYear
2013
fDate
5-10 Jan. 2013
Firstpage
262
Lastpage
266
Abstract
In this paper we analyze the impact of power supply noise on clock jitter in high-speed DDR memory interfaces. Random system failures on a custom IC were traced to excessive clock jitter on the DDR output clock, which when debugged were attributed to power supply noise caused at certain frequency bands (between ~30 and ~100MHz). We present methods that have been used at the architectural and system levels and in physical design to alleviate the effect of the supply noise on the DDR clock.
Keywords
DRAM chips; clocks; failure analysis; integrated circuit design; integrated circuit noise; power supply circuits; timing jitter; DDR output clock; clock jitter; high-speed DDR memory interfaces; physical design; power supply noise; random system failures; Clocks; Digital signal processing; Impedance; Jitter; Noise; Power supplies; Switches; Clock jitter; power delivery network; power supply noise;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on
Conference_Location
Pune
ISSN
1063-9667
Print_ISBN
978-1-4673-4639-9
Type
conf
DOI
10.1109/VLSID.2013.198
Filename
6472650
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