DocumentCode :
3477996
Title :
Hardware-corroborated Variability-Aware SRAM Methodology
Author :
Joshi, Rajan ; Kanj, Rouwaida ; Butt, Steven ; Acar, Esra ; Lea, D. ; Sciacca, D.
Author_Institution :
IBM TJ Watson Res. Labs., Yorktown Heights, NY, USA
fYear :
2013
fDate :
5-10 Jan. 2013
Firstpage :
344
Lastpage :
349
Abstract :
The paper presents a novel hardware-measurement based methodology to extract within-product-array variability as opposed to kerf. The methodology was applied to a 45nm 2.4Mb SRAM design with emphasis on critical dimension measurements. Local mismatch and spatial variations, LER effects and backend effects were measured. Lithographic models were tuned to the 45nm process. Statistically measured variability in critical process units along with extracted long-range CD variation through lithography simulations were then fed to a newly developed statistical engine to predict design yield, leakage and performance. The predicted yield results were then corroborated with the hardware providing feedback for process tuning. In addition to monitoring mature processes, such hardware measurement techniques can also be used to monitor or decipher yield-detractor defects.
Keywords :
SRAM chips; lithography; LER effects; backend effects; decipher yield-detractor defects; hardware measurement techniques; hardware-corroborated variability-Aware SRAM design methodology; lithographic model; lithography simulations; long-range CD variation extraction; size 45 nm; spatial variations; Arrays; Delay; Hardware; Lithography; Random access memory; Semiconductor device measurement; Systematics; Critical Dimension; Design for Manufacturability; Global mismatch; Local mismatch; Yield;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on
Conference_Location :
Pune
ISSN :
1063-9667
Print_ISBN :
978-1-4673-4639-9
Type :
conf
DOI :
10.1109/VLSID.2013.212
Filename :
6472664
Link To Document :
بازگشت