• DocumentCode
    3478031
  • Title

    Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy

  • Author

    Save, Y.D. ; Narayanan, H. ; Patkar, Sachin B.

  • Author_Institution
    Indian Inst. of Technol., Mumbai, Mumbai, India
  • fYear
    2013
  • fDate
    5-10 Jan. 2013
  • Firstpage
    356
  • Lastpage
    361
  • Abstract
    The paper describes a method to improve the performance of the Two Graph based circuit simulator in order to solve very large size circuits arising out of an electrical analogy for Partial Differential Equations (PDEs). The method is based on a memory efficient implementation of the linear solver with the Two graph method on Graphics processors (GPU). We have built simulators based on the Two Graph method with different linear system solvers, direct (Cholesky) and iterative (Conjugate Gradient (CG)) solvers, for solution of PDEs through the electrical analogy and compared the performance with simulators based on MNA and different LU solvers. The use of Cholesky and CG solvers would not be feasible with MNA. The comparison reveals that the iterative solver based simulator is suitable for large size circuits due to its reduced memory requirement. The memory requirement of the simulator is further lowered by an implicit implementation of the iterative solver with the Two Graph method (without storing the system matrix representing electrical equations). But this increases the computational time. The timing performance of the simulator is improved by an efficient implementation of the implicit CG method on GPU. Using this method, we have been able to simulate circuits arising from Poisson equations with approximately 5 million nodes and 20 million edges in less than 12 minutes using 3.2 GB memory.
  • Keywords
    Poisson equation; circuit simulation; conjugate gradient methods; graphics processing units; iterative methods; Cholesky solver; GPU; PDE-electrical analogy; Poisson equations; conjugate gradient solver; direct solver; graphics processors; iterative solver; linear system solvers; memory efficient implementation; memory requirement; memory size 3.2 GByte; partial differential equations; two graph based circuit simulator; Equations; Graphics processing units; Mathematical model; Memory management; Sparse matrices; Symmetric matrices; Transmission line matrix methods; Circuit Simulator; Conjugate Gradient (CG); Electrical Analogy; GPU; Partial Differential Equations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on
  • Conference_Location
    Pune
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-4673-4639-9
  • Type

    conf

  • DOI
    10.1109/VLSID.2013.214
  • Filename
    6472666