DocumentCode :
34781
Title :
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL
Author :
Ferriss, Mark ; Plouchart, J.-O. ; Natarajan, Arutselvan ; Rylyakov, A. ; Parker, Brendon ; Tierno, Jose ; Babakhani, A. ; Yaldiz, Soner ; Valdes-Garcia, A. ; Sadhu, B. ; Friedman, Daniel
Author_Institution :
IBM T. J. Watson Research Center, Yorktown Heights,
Volume :
48
Issue :
4
fYear :
2013
fDate :
Apr-13
Firstpage :
996
Lastpage :
1008
Abstract :
An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO\´s small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of 
126.5 dBc/Hz at 20.1 GHz and 124.2 dBc/Hz at 24 GHz
Keywords :
Capacitors; Charge pumps; Phase locked loops; Phase noise; Transfer functions; Voltage-controlled oscillators; Bandwidth calibration; PLL; frequency synthesizers; phase locked loop;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2013.2239114
Filename :
6423804
Link To Document :
