A power-efficient 14-bit 250MS/s pipelined ADC

A power-efficient 14-bit 250MS/s pipelined ADC is presented. With the aid of range-scaling technique, an original single-stage opamp is adopted to replace the conventional large-swing opamp. A novel charge compensation based (CCB) technique effectively reduces input-dependent errors of the reference voltage and it consumes no static current. Total power is reduced further because of opamp sharing, capacitor sharing and removing the dedicated sample-and-hold amplifier (SHA). Besides, the calibration is employed to correct linearity errors. This ADC is designed in a 55nm CMOS process with a 1.2-V supply voltage. CCB reference improves SNDR/SFDR by more than 4 dB/10 dB and stabilizes the performance. The simulation result with noise shows that the ADC has the SNDR/SFDR of 71.2 dB/86 dBc at 119 MHz input frequency. The ADC consumes 36.2 mW, which includes 23 mW for the ADC core and 12 mW for the low jitter clock receiver. It achieves the figure of merit (FOM) of 48.6 fJ/step.