DocumentCode
3478525
Title
A new low-power CMOS dynamic logic circuit
Author
Song Jia ; Shigong Lyu ; Qinglong Meng ; Fengfeng Wu ; Heqing Xu
Author_Institution
Key Lab. of Microelectron. Devices & Circuits (MoE), Peking Univ., Beijing, China
fYear
2013
fDate
3-5 June 2013
Firstpage
1
Lastpage
2
Abstract
A new design of half pre-charged CMOS dynamic logic circuit is proposed in this paper. By adding a transmission transistor and a pre-charge transistor along with an optimization of the comparator structure, the DC short circuits during pre-charge and evaluation phases are both eliminated, which in turn reduced the overall power consumption significantly. Simulation results show that for a two input AND gate dynamic logic, the proposed circuit can lower power consumption by 90% compared to the reference design.
Keywords
CMOS logic circuits; MOSFET; comparators (circuits); low-power electronics; optimisation; power consumption; DC short circuits; comparator structure optimization; low-power CMOS dynamic logic circuit; power consumption; transmission transistor; two input AND gate dynamic logic; CMOS integrated circuits; MOS devices; CMOS dynamic logic; comparator optimization; half pre-charge; low power;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of
Conference_Location
Hong Kong
Type
conf
DOI
10.1109/EDSSC.2013.6628224
Filename
6628224
Link To Document