A scaled CMOS-compatible smart power IC technology

Author

Wong, S.L. ; Kim, M.J. ; Young, J.C. ; Mukherjee, S.

Author_Institution

Philips Lab., Briarcliff Manor, NY, USA

fYear

1991

fDate

22-24 Apr 1991

Firstpage

51

Lastpage

55

Abstract

An integrated VDMOS-based PIC process was developed to increase the cost effectiveness and performance of 60 V high current circuits. Compact 60 V CMOS elements and a 140 mΩ-mm² VDMOS were integrated into a 3 μm CMOS process using only one additional mask. This increased level of integration allowed the use of a cell-based ASPIC (application-specific power IC) methodology as an attractive alternative to conventional full-custom approaches. This was demonstrated in the development of a 10 A intelligent power switch for automotive applications

Keywords

CMOS integrated circuits; application specific integrated circuits; automotive electronics; power integrated circuits; semiconductor switches; 10 A; 3 micron; 60 V; CMOS-compatible; VDMOS based process; application-specific power IC; automotive applications; cell-based ASPIC; high current circuits; intelligent power switch; scaled technology; smart power IC technology; Automobiles; Automotive engineering; CMOS process; CMOS technology; Costs; Electric breakdown; Intelligent vehicles; Laboratories; Power integrated circuits; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1991. ISPSD '91., Proceedings of the 3rd International Symposium on

Conference_Location

Baltimore, MD

ISSN

1063-6854

Print_ISBN

0-7803-0009-2

Type

conf

DOI

10.1109/ISPSD.1991.146065

Filename

146065